A phase-lock loop ("PLL") is typically used to generate an output signal after acquiring the frequency and the phase of a reference clock for purposes of synchronization. Although the frequency of the output signal is ultimately locked onto the frequency of the reference clock, there exists a static phase error between the reference clock and the output signal. FIG. 1 shows a block diagram of a conventional PLL. PLL 100 includes a phase comparator 110 coupled to receive a reference clock from a lead 105. Outputs from phase comparator 110 are provided to a charge pump 120 via leads 115 and 117. An output of charge pump 120 is provided to both a loop filter 130 and a voltage-controlled oscillator ("VCO") 140. An output signal from VCO 140 is provided to a divide by N circuit 150. The output of divide by N circuit 150 is provided as feedback to phase comparator 110. Eventually, the output signal from VCO 140 will have a static phase error relative to the reference clock.
Sources of static phase error are charge injection, loop filter leakage and pump up/down current mismatch. The pump up/down current mismatch can be illustrated by reference to FIG. 2. Circuit 120' is included in charge pump 120 of FIG. 1. Circuit 120' includes a current mirror 200 that includes transistors 210, 220 and a current sink 230. Circuit 120' also includes a current mirror 240 that includes transistors 250, 260 and a current source 270. Current mirrors 200, 240 are coupled to switches 280, 290, respectively. Switches 280, 290 are coupled to charge pump 120 (FIG. 1) via leads 115, 117, respectively. An output is provided at node 285. A loop filter, such as loop filter 130 in FIG. 1, is coupled to node 285.
Accumulated errors can cause the currents of current sink 230 and current source 270 to mismatch. Such errors are caused by process variations, ambient conditions and inherent device characteristics. This mismatch can cause static phase errors and gain error. Thus, a need exists for a charge pump that reduces current mismatch to reduce static phase error. The present invention meets this need.